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? semiconductor components industries, llc, 2004 may, 2004 ? rev. 6 1 publication order number: mmdf2c03hd/d mmdf2c03hd preferred device power mosfet 2 amps, 30 volts complementary so?8, dual these miniature surface mount mosfets feature ultra low r ds(on) and true logic level performance. they are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a very low reverse recovery time. minimos devices are designed for use in low voltage, high speed switching applications where power efficiency is important. typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. they can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. the avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. ? ultra low r ds(on) provides higher efficiency and extends battery life ? logic level gate drive ? can be driven by logic ics ? miniature so-8 surface mount package ? saves board space ? diode is characterized for use in bridge circuits ? diode exhibits high speed, with soft recovery ? i dss specified at elevated temperature ? avalanche energy specified ? mounting information for so-8 package provided maximum ratings (t j = 25 c unless otherwise noted) (note 1) rating symbol value unit drain?to?source voltage v dss 30 vdc gate?to?source voltage v gs 20 vdc drain current ? continuous n?channel p?channel drain current ? pulsed n?channel p?channel i d i dm 4.1 3.0 21 15 a operating and storage temperature range t j , t stg ?55 to 150 c total power dissipation @ t a = 25 c (note 2) p d 2.0 watts thermal resistance ? junction to ambient (note 2) r q ja 62.5 c/w single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 30 v, v gs = 5.0 v, peak i l = 9.0 apk, l = 8.0 mh, r g = 25 w ) n?channel (v dd = 30 v, v gs = 5.0 v, peak i l = 6.0 apk, l = 18 mh, r g = 25 w ) p?channel e as 324 324 mj maximum lead temperature for soldering, 0.0625 from case. time in solder bath is 10 seconds. t l 260 c 1. negative signs for p?channel device omitted for clarity. 2. mounted on 2o square fr4 board (1o sq. 2 oz. cu 0.06o thick single sided) with one die operating, 10 sec. max. n?source 1 2 3 4 8 7 6 5 top view n?gate p?source p?gate n?drain n?drain p?drain p?drain device package shipping 2 ordering information MMDF2C03HDR2 so?8 2500 tape & reel n?channel marking diagram d s g pin assignment preferred devices are recommended choices for future use and best overall value. d s g p?channel 2 amperes 30 volts r ds(on) = 70 m (n-channel) r ds(on) = 200 m (p-channel) http://onsemi.com so?8 case 751 style 14 1 8 d2c03 alyw 1 8 d2c03 = device code a = assembly location l = wafer lot y = year w = work week 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
mmdf2c03hd http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) (note 3) characteristic symbol polarity min typ max unit off characteristics drain?source breakdown voltage (v gs = 0 vdc, i d = 250 adc) v (br)dss ? 30 ? ? vdc zero gate voltage drain current (v ds = 30 vdc, v gs = 0 vdc) i dss (n) (p) ? ? ? ? 1.0 1.0 adc gate?body leakage current (v gs = 20 vdc, v ds = 0) i gss ? ? ? 100 nadc on characteristics (note 4) gate threshold voltage (v ds = v gs , i d = 250 adc) v gs(th) (n) (p) 1.0 1.0 1.7 1.5 3.0 2.0 vdc drain?to?source on?resistance (v gs = 10 vdc, i d = 3.0 adc) (v gs = 10 vdc, i d = 2.0 adc) r ds(on) (n) (p) ? ? 0.06 0.17 0.070 0.200 ohm drain?to?source on?resistance (v gs = 4.5 vdc, i d = 1.5 adc) (v gs = 4.5 vdc, i d = 1.0 adc) r ds(on) (n) (p) ? ? 0.065 0.225 0.075 0.300 ohm forward transconductance (v ds = 3.0 vdc, i d = 1.5 adc) (v ds = 3.0 vdc, i d = 1.0 adc) g fs (n) (p) 2.0 2.0 3.6 3.4 ? ? mhos dynamic characteristics input capacitance c iss (n) (p) ? ? 450 397 630 550 pf output capacitance (v ds = 24 vdc, v gs = 0 vdc, f = 1.0 mhz) c oss (n) (p) ? ? 160 189 225 250 transfer capacitance c rss (n) (p) ? ? 35 64 70 126 switching characteristics (note 5) turn?on delay time ( v dd = 15 vdc, i d = 3.0 adc, t d(on) (n) (p) ? ? 12 16 24 32 ns rise time (v dd = 15 vdc , i d = 3 . 0 adc , v gs = 4.5 vdc, r g = 9.1 w ) t r (n) (p) ? ? 65 18 130 36 turn?off delay time (v dd = 15 vdc, i d = 2.0 adc, v gs = 4.5 vdc, t d(off) (n) (p) ? ? 16 63 32 126 fall time v gs = 4 . 5 vdc , r g = 6.0 w ) t f (n) (p) ? ? 19 194 38 390 turn?on delay time ( v dd = 15 vdc, i d = 3.0 adc, t d(on) (n) (p) ? ? 8.0 9.0 16 18 rise time (v dd = 15 vdc , i d = 3 . 0 adc , v gs = 10 vdc, r g = 9.1 w ) t r (n) (p) ? ? 15 10 30 20 turn?off delay time (v dd = 15 vdc, i d = 2.0 adc, v gs = 10 vdc, t d(off) (n) (p) ? ? 30 81 60 162 fall time v gs = 10 vdc , r g = 6.0 w ) t f (n) (p) ? ? 23 192 46 384 3. negative signs for p?channel device omitted for clarity. 4. pulse test: pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperature.
mmdf2c03hd http://onsemi.com 3 electrical characteristics ? continued (t a = 25 c unless otherwise noted) (note 6) characteristic symbol polarity min typ max unit switching characteristics ? continued (note 8) total gate charge q t (n) (p) ? ? 11.5 14.2 16 19 nc gate?source charge (v ds = 10 vdc, i d = 3.0 adc, v gs = 10 vdc) q 1 (n) (p) ? ? 1.5 1.1 ? ? gate?drain charge (v ds = 24 vdc, i d = 2.0 adc, v gs = 10 vdc) q 2 (n) (p) ? ? 3.5 4.5 ? ? v gs = 10 vdc) q 3 (n) (p) ? ? 2.8 3.5 ? ? source?drain diode characteristics (t c = 25 c) forward voltage (note 7) (i s = 3.0 adc, v gs = 0 vdc) (i s = 2.0 adc, v gs = 0 vdc) v sd (n) (p) ? ? 0.82 1.82 1.2 2.0 vdc reverse recovery time t rr (n) (p) ? ? 24 42 ? ? ns (i f =i s t a (n) (p) ? ? 17 16 ? ? (i f = i s , di s /dt = 100 a/ s) t b (n) (p) ? ? 7.0 26 ? ? reverse recovery storage charge q rr (n) (p) ? ? 0.025 0.043 ? ? c 6. negative signs for p?channel device omitted for clarity. 7. pulse test: pulse width 300 m s, duty cycle 2%. 8. switching characteristics are independent of operating junction temperature.
mmdf2c03hd http://onsemi.com 4 typical electrical characteristics n?channel p?channel 3.9 v figure 1. on?region characteristics figure 2. transfer characteristics figure 1. on?region characteristics figure 2. transfer characteristics 0 0.4 0.8 1.2 1.6 2 0 1 3 v ds , drain-to-source voltage (volts) i d , drain current (amps) 4 2 t j = 25 c 2.7 v 0.2 0.6 1.8 1.4 1 5 6 2.5 v 2.9 v 3.1 v 3.3 v 3.5 v 3.7 v 4.5 v 4.3 v 3.9 v 4.1 v v gs = 10 v 0 i d , drain current (amps) v gs , gate-to-source voltage (volts) v ds 10 v 25 c 2 4 6 5 1 2 2.5 3 3.5 4 3 0 0.2 0.4 0.6 0.8 2 0 2 3 4 v ds , drain-to-source voltage (volts) i d , drain current (amps) t j = 25 c v gs = 10 v 1 1.2 2.7 v 2.5 v 1 1.4 1.6 1.8 1.5 1.7 1.9 2.1 2.3 3.7 0 2 3 4 i d , drain current (amps) v gs , gate-to-source voltage (volts) v ds 10 v t j = 100 c 25 c -55 c 2.5 1 2.7 2.9 3.1 3.3 3.5 t j = 100 c -55 c 2.9 v 3.1 v 3.3 v 3.5 v 3.7 v 4.5 v
mmdf2c03hd http://onsemi.com 5 typical electrical characteristics figure 3. on?resistance versus gate?to?source voltage figure 4. on?resistance versus drain current and gate voltage figure 5. on?resistance variation with temperature figure 3. on?resistance versus gate?to?source voltage figure 4. on?resistance versus drain current and gate voltage figure 5. on?resistance variation with temperature r ds(on) , drain-to-source resistance (ohms) 0.4 0.5 0.6 0.3 0.1 0.2 0 2345 8 67 910 v gs , gate-to-source voltage (volts) i d = 1.5 a t j = 25 c r ds(on) , drain-to-source resistance (ohms) 0.05 i d , drain current (amps) 0.08 0 0.5 1 2.5 3 0.06 0.07 1.5 2 10 v v gs = 4.5 t j = 25 c r ds(on) , drain-to-source resistance (normalized) t j , junction temperature ( c) -50 0 50 100 150 0 0.5 1.0 1.5 2.0 v gs = 10 v i d = 1.5 a 125 75 25 -25 v gs , gate-to-source voltage (volts) i d , drain current (amps) r ds(on) , drain-to-source resistance (ohms) 0 0.5 1 1.5 2 4 0.10 0.15 0.20 0.25 0.30 t j = 25 c v gs = 4.5 v 2.5 3 3.5 10 v r ds(on) , drain-to-source resistance (ohms) 01 2 3 4 10 0 0.1 0.3 0.4 0.6 i d = 1 a t j = 25 c 0.2 56789 0.5 r ds(on) , drain-to-source resistance t j , junction temperature ( c) -50 0 50 100 150 0.6 v gs = 10 v i d = 2 a 1.4 (normalized) -25 25 75 125 0.8 1.6 1.2 1.0 n?channel p?channel
mmdf2c03hd http://onsemi.com 6 typical electrical characteristics n?channel p?channel figure 6. drain?to?source leakage current versus voltage figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) 1 100 v ds , drain-to-source voltage (volts) 10 0 5 10 15 30 20 25 v gs = 0 v t j = 125 c 100 c 0102030 10 100 1000 v ds , drain-to-source voltage (volts) i dss , leakage (na) v gs = 0 v t j = 125 c 100 c 51525 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses.
mmdf2c03hd http://onsemi.com 7 figure 7. capacitance variation figure 7. capacitance variation c, capacitance (pf) 10 0 10 15 25 t j = 25 c v ds = 0 v v gs = 0 v 1000 800 600 400 200 0 20 c iss c oss c rss 55 c iss c rss 30 1200 gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) 400 600 800 1200 1000 10 0 10 15 20 30 v gs v ds 55 c rss t j = 25 c 200 25 c iss v ds = 0 v v gs = 0 v c iss c oss c rss 0 gate-to-source or drain-to-source voltage (volts) v gs v ds n?channel p?channel figure 8. gate?to?source and drain?to?source voltage versus total charge figure 9. resistive switching time variation versus gate resistance figure 8. gate?to?source and drain?to?source voltage versus total charge figure 9. resistive switching time variation versus gate resistance v gs , gate-to-source voltage (volts) q g , total gate charge (nc) 02 4 6 8 i d = 3 a t j = 25 c v gs 6 3 0 12 9 24 18 12 6 0 v ds qt q1 q2 q3 10 12 t, time (ns) r g , gate resistance (ohms) 1000 1 100 10 1 v dd = 15 v i d = 3 a v gs = 10 v t j = 25 c t d(on) t r 100 10 t d(off) t f 24 v gs , gate-to-source voltage (volts) 20 16 12 8 4 0 0 10 6 2 0 12 8 4 24 6 8 16 i d = 2 a t j = 25 c 10 12 14 v ds v gs qt q2 q3 q1 r g , gate resistance (ohms) 1 10 100 1000 100 10 1 t, time (ns) v dd = 15 v i d = 2 a v gs = 10 v t j = 25 c t r t f t d(off) t d(on) q g , total gate charge (nc) v ds , drain-to-source voltage (volts)
mmdf2c03hd http://onsemi.com 8 drain?to?source diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 15. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. figure 10. diode forward voltage versus current figure 10. diode forward voltage versus current i s , source current (amps) v sd , source-to-drain voltage (volts) 1.0 1.5 2.0 3.0 2.5 0.5 0.55 0 0.5 t j = 25 c v gs = 0 v 0.6 0.65 0.7 0.75 0.8 0.85 0.5 0.7 0.9 1.1 1.3 1.9 0 0.4 1.2 1.6 2 v sd , source-to-drain voltage (volts) i s , source current (amps) 0.8 1.5 1.7 t j = 25 c v gs = 0 v n?channel p?channel
mmdf2c03hd http://onsemi.com 9 i s , source current t, time di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr figure 11. reverse recovery time (t rr ) safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance ? general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 13). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. figure 12. maximum rated forward biased safe operating area figure 12. maximum rated forward biased safe operating area 0.1 v ds , drain-to-source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 20 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2 sq. fr4 board (1 sq. 2 oz. cu 0.06 thick single sided) with one die operating, 10s max. 1 ms 100 m s 0.1 v ds , drain-to-source voltage (volts) 1 10 i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 v gs = 20 v single pulse t c = 25 c 10 0.1 dc 10 ms 1 100 100 mounted on 2 sq. fr4 board (1 sq. 2 oz. cu 0.06 thick single sided) with one die operating, 10s max. 1 ms 100 m s 10 m s n?channel p?channel n?channel p?channel
mmdf2c03hd http://onsemi.com 10 figure 13. maximum avalanche energy versus starting junction temperature figure 13. maximum avalanche energy versus starting junction temperature t j , starting junction temperature ( c) e as , single pulse drain-to-source avalanche energy (mj) 0 25 50 75 100 125 150 i d = 9 a 250 150 350 100 50 200 300 t j , starting junction temperature ( c) e as , single pulse drain-to-source avalanche energy (mj) 0 25 50 75 100 125 150 50 i d = 6 a 250 350 100 200 300 150 typical electrical characteristics di/dt t rr t a t p i s 0.25 i s time i s t b figure 14. thermal response figure 15. diode reverse recovery waveform t, time (s) rthja(t), effective transient thermal resistance 1 0.1 0.01 d = 0.5 single pulse 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.2 0.1 0.05 0.02 0.01 1.0e+02 1.0e+03 0.001 10 0.0175 w 0.0710 w 0.2706 w 0.5776 w 0.7086 w 107.55 f 1.7891 f 0.3074 f 0.0854 f 0.0154 f chip ambient normalized to q ja at 10s.
mmdf2c03hd http://onsemi.com 11 package dimensions so?8 case 751?07 issue ab seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 style 14: pin 1. n?source 2. n?gate 3. p?source 4. p?gate 5. p?drain 6. p?drain 7. n?drain 8. n?drain
mmdf2c03hd http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mmdf2c03hd/d minimos is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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